EFR32 : SOC Transceiver Module With Arm Cortex 4 & High Sensitivity DSSS
The EFR32 module is our latest low-power, high-performance wireless communication module(SOC transceiver module). It is developed based on SILICON’s EFR32FG14. It adopts advanced direct sequence spread spectrum communication modulation technology (DSSS), and higher performance 32-bit ARM®Cortex®-M4.
SOC transceiver module EFR32 is easy in the secondary development of the module. The traditional wireless module is that the wireless transceiver chip and the MCU are independent of each other, and the MCU needs to control the wireless transceiver chip to transmit data wirelessly through SPI/IIC and other methods. The secondary development of EFR32 directly skips this cumbersome step, and can call the wireless library function when using the wireless function, which greatly accelerates the development progress.
12-bit 1Msps sampling high-speed and high-precision SARADC
Two 16-bit timers/counters
One 32-bit timer/counter
One 32-bit RTC timer
2 watchdog timers
16 general-purpose I/O pins
128K bytes Flash memory
16K bytes RAM memory
2 UART standard communication interface
1 LPUART low-power communication interface
8-channel DMA controller
Digital-to-analog current converter (IDAC)
Working temperature range: -40℃~+85℃
1.8V-3.8V power supply
Integrated power amplifier, the highest transmit power is 22.9 dBm (Sub-GHz)
Support multiple transmission protocols such as DSSS, GFSK, OOK, MSK, etc.
Support multiple modulation formats such as Wireless M-Bus, IEEE 802.15.4g SUN-FSK PHYs, etc.
Applications of SOC Transceiver Module EFR32
Home and building automation and security
Commercial and retail lighting and sensing
Automated industry
Electronic shelf label
Remote meter reading
Pin number
Pin definition
I/O
Description
1
PC10
I/O
GPIO pin
2
PC11
I/O
GPIO pin
3
PF0
I/O
GPIO pin
4
PF1
I/O
GPIO pin
5
PF2
I/O
GPIO pin
6
PF3
I/O
GPIO pin,TCXO
7
RESET
I
Reset input, active low. To apply an external reset source to this pin, it is only necessary to drive the pin low during reset and let the internal pull-up circuit ensure that the reset is released.
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